In the last 20 years, miniaturization has driven the improvement of chip performance, and the resulting boom in consumer electronics. In the last 10 years, this strategy has been combined with the implementation of novel materials such as insulators, to increase speed, reduce power consumption, protect wiring from short circuits and electrical interference.
Just as the chips shrink, the conducting wires get smaller and closer to each other. This means the insulator has to keep pace. The typical solution adopted by the chip industry has been to introduce air (an excellent insulator) in the form of extremely small bubbles or “pores” (1/100,000 the size of a human hair) into the insulator – making the chip surface look like Swiss cheese.
Solving the insulation problem with plasma
Unfortunately, many more air bubbles are needed to reach the desired insulating properties in the most advanced microprocessors in enterprise or consumer applications. This produces an insulator that resembles more of an air-tunnel network instead of a Swiss cheese-type structure.
To compound the problem of air tunneling, a chip’s wiring damages the insulator by penetrating these air channels. This damages the insulator – reducing its insulating properties.
Post Porosity Plasma Protection solves this issue by overcoming power leakage problems at near-atomic design nodes, and shields semiconductor chips from severe physical and structural damage during the wire patterning and processing steps during manufacturing.
The technique uses the absence of matter in absorbent material to form between the chip’s wires, allowing electrical signals to flow faster while consuming less electrical power. Once the electrical wiring is put in place, the “sunscreen” is removed by simply heating the structure, thus liberating the undamaged air channels.
If you’re in the Bay Area on April 10, come to the Materials Research Society Show at the Moscone West Convention Center and we’ll tell you all about it!